With constant down-scaling and increasingly demanding requirements to the speed and functionality of ultra-high density integrated circuits, the integration of resistors and capacitors into prior art semiconductor structures becomes increasingly problematic. Resistors are most often integrated into a semiconductor structure during middle of the line (MOL) process flow. The MOL process flow generally includes those set of process steps used in the creation of the gate (CA) contacts and the source/drain (CB) contacts of transistors. Capacitors are typically formed in the back end of line (BEOL) process flow of a semiconductor structure. The BEOL process flow generally includes the process steps used in the formation of the several layers of metal interconnect lines used to provide the electrical connections to devices on the substrate of a semiconductor structure.
Prior art semiconductor structures require a dielectric layer disposed between the gate structure of the transistors and the resistors in order to prevent the resistors from electrically shorting to the gate. Problematically however, this increases the thickness of the dielectric layers in the MOL architecture, which exacerbates dimensional changes in width between the top and bottom of the CA and CB contacts. This is due to the fact that etching is never completely in a vertical direction. That is, any etching process (even an anisotropic RIE etch process) will always have some horizontal etch component to it. Accordingly, the top of a CA or a CB contact will always be larger than the bottom. The thicker the dielectric layers that must be etched through in order to form the CA and CB contacts, the greater the dimensional changes that will occur. These dimensional changes can have a negative effect on quality and reliability.
Also problematically in prior art semiconductor devices, the transistors and other like devices over which a resistor is disposed are rendered non-functional or disabled. This is because the resistor prevents any electrical connections from reaching the components disposed underneath them. So a Fin Field Effect Transistor (FinFET), for example, which can be made operational with CA contacts to its gate and CB contacts to its source/drain regions, is rendered non-functional if it is covered by a resistor that blocks such contacts from being made. Moreover, resistors generally have an increasingly large foot print and tend to cover larger number of devices with scaling due to the fact that their resistivity is fixed.
Capacitors also take up room in the BEOL semiconductor structure and are increasingly difficult to down-scale. Additionally, conventional process flow requires at least a single mask to form resistors in the MOL and at least two separate masks to form capacitors in the FEOL of a semiconductor structure. The use of such multiple masks adds cost and complexity to the manufacturing process of a semiconductor structure.
Accordingly, there is a need for a semiconductor structure that does not require a dielectric layer between resistors and gates in order to prevent electrical shorting. Additionally there is a need for a semiconductor structure wherein the resistors do not disable the components disposed below them, and can be used to form further devices over the transistor. Additionally, there is a need for a method to reduce the number of masks used to form resistors and capacitors in a semiconductor structure.